| PART |
Description |
Maker |
| HD74HC108 HD74HC108P |
Dual J-K Flip-Flops (with Preset/ Common Clear and Common Clock)
Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)
FLIP-FLOP|DUAL|J/K TYPE|HC-CMOS|DIP|14PIN|PLASTIC
|
HITACHI[Hitachi Semiconductor]
|
| AS7C32098A AS7C32098A-20TIN AS7C32098A-10TC AS7C32 |
Hex D-Type Flip-Flops With Clear 16-TSSOP -40 to 85 128K X 16 STANDARD SRAM, 10 ns, PDSO44
Quadruple D-Type Flip-Flops With Clear 16-TVSOP -40 to 85
Quadruple D-Type Flip-Flops With Clear 16-SSOP -40 to 85
Quadruple D-Type Flip-Flops With Clear 16-SOIC -40 to 85
Quadruple D-Type Flip-Flops With Clear 16-SO -40 to 85
SRAM - 3.3V Fast Asynchronous
3.3 V 128K x 16 CMOS SRAM
|
Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
|
| 74LVX112M 74LVX112MTC 74LVX112 74LVX112SJX |
J-K-Type Flip-Flop
Low Voltage Dual J-K Flip-Flops with Preset and Clear
From old datasheet system
|
FAIRCHILD[Fairchild Semiconductor]
|
| TC311 TC312 TSC311 |
(TSC311 - TSC313) Flip Flops
(TC311 - TC313) FLIP FLOPS
|
Sertech
|
| HD74HC73P HD74HC73FPEL HD74HC73RPEL |
Dual J-K Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| HD74HC107 HD74HC107P HD74HC107RPEL HD74HC107FPEL |
Dual J-K Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| HD74ALVCH16820 |
3.3-V 10-bit Flip Flops with Dual Outputs
|
Renesas Electronics Corporation
|
| HD74LV74A HD74LV74AFPEL HD74LV74ARPEL HD74LV74ATEL |
Dual D-type Flip Flops with Preset and Clear
|
Renesas Electronics Corporation
|
| HD74HC74FPEL HD74HC74TELL HD74HC74 HD74HC74P |
Dual D-type Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| U74LVC74AG-S14-R |
DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS
|
Unisonic Technologies
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
